Energy-aware variable partitioning and instruction scheduling for multibank memory architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Variable partitioning for dual memory bank DSPs
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Architecting phase change memory as a scalable dram alternative
Proceedings of the 36th annual international symposium on Computer architecture
A durable and energy efficient main memory using phase change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
Scalable high performance main memory system using phase-change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
PDRAM: a hybrid PRAM and DRAM main memory system
Proceedings of the 46th Annual Design Automation Conference
Proceedings of the 47th Design Automation Conference
Operating system support for NVM+DRAM hybrid main memory
HotOS'09 Proceedings of the 12th conference on Hot topics in operating systems
Efficient variable partitioning and scheduling for DSP processors with multiple memory modules
IEEE Transactions on Signal Processing
Emerging non-volatile memories: opportunities and challenges
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Optimal task allocation on non-volatile memory based hybrid main memory
Proceedings of the 2011 ACM Symposium on Research in Applied Computation
Proceedings of the 49th Annual Design Automation Conference
Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache
Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems
Static and dynamic co-optimizations for blocks mapping in hybrid caches
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Write activity reduction on non-volatile main memories for embedded chip multiprocessors
ACM Transactions on Embedded Computing Systems (TECS)
Compiler directed write-mode selection for high performance low power volatile PCM
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Software enabled wear-leveling for hybrid PCM main memory on embedded systems
Proceedings of the Conference on Design, Automation and Test in Europe
ACM Transactions on Embedded Computing Systems (TECS)
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In this paper, we utilize a hybrid main memory composed of DRAM and Phase Change Random Access Memory (PRAM) for DSP systems, which leverages the low power consumption of PRAM while minimizing the performance and endurance degradation caused by write operations on PRAM. We re-consider the variable partitioning problem on this hybrid main memory. Different objectives, for example power consumption and the number of writes on PRAM, are considered in this paper. By using the proposed models and algorithms, experiments show that we can reduce 53% power consumption and 79% the number of writes on PRAM on average, compared with pure DRAM and pure PRAM memory, respectively.