Cache coherence enabled adaptive refresh for volatile STT-RAM

Authors:
Jianhua Li;Liang Shi;Qing'an Li;Chun Jason Xue;Yiran Chen;Yinlong Xu
Affiliations:
City University of Hong Kong, Hong Kong and University of Science & Technology of China, China;City University of Hong Kong, Hong Kong and University of Science & Technology of China, China;City University of Hong Kong, Hong Kong and Wuhan University, Wuhan, China;City University of Hong Kong, Hong Kong;University of Pittsburgh;University of Science & Technology of China, China
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2013

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Abstract

Spin-Transfer Torque RAM (STT-RAM) is extensively studied in recent years. Recent work proposed to improve the write performance of STT-RAM through relaxing the retention time of STT-RAM cell, magnetic tunnel junction (MTJ). Unfortunately, frequent refresh operations of volatile STT-RAM could dissipate significantly extra energy. In addition, refresh operations can severely conflict with normal read/write operations and results in degraded cache performance. This paper proposes Cache Coherence Enabled Adaptive Refresh (CCear) to minimize refresh operations for volatile STT-RAM. Through novel modifications to cache coherence protocol, CCear can effectively minimize the number of refresh operations on volatile STT-RAM. Full-system simulation results show that CCear approaches the performance of the ideal refresh policy with negligible overhead.