Effect of SiO2 tunnel layer processes on the characteristics of MONOS charge trap devices with poly-Si channels

  • Authors:

  • Heedo Na;Jinho Oh;Kyumin Lee;Jonggi Kim;Sunghoon Lee;Dong Hyeok Lim;Mann-Ho Cho;Hyunchul Sohn

  • Affiliations:

  • Department of Materials Science and Engineering, Yonsei University, 50 Yonsei-ro, Seodaemun-gu, Seoul 120-749, Republic of Korea;Department of Materials Science and Engineering, Yonsei University, 50 Yonsei-ro, Seodaemun-gu, Seoul 120-749, Republic of Korea;Department of Materials Science and Engineering, Yonsei University, 50 Yonsei-ro, Seodaemun-gu, Seoul 120-749, Republic of Korea;Department of Materials Science and Engineering, Yonsei University, 50 Yonsei-ro, Seodaemun-gu, Seoul 120-749, Republic of Korea;R&D Division, SK hynix Semiconductor Inc., San 136-1 Ami-ri, Bubal-eub, Icheon-si, Gyeonggi-do 467-701, Republic of Korea;Institute of Physics and Applied Physics, Yonsei University, 50 Yonsei-ro, Seodaemun-gu, Seoul 120-749, Republic of Korea;Institute of Physics and Applied Physics, Yonsei University, 50 Yonsei-ro, Seodaemun-gu, Seoul 120-749, Republic of Korea;Department of Materials Science and Engineering, Yonsei University, 50 Yonsei-ro, Seodaemun-gu, Seoul 120-749, Republic of Korea

  • Venue:
  • Microelectronic Engineering
  • Year:
  • 2013

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Abstract

In this study, we investigated the effect of various SiO"2 tunnel layers on the characteristics of charge trap memories with Metal/SiO"2/Si"3N"4/SiO"2/n-type poly-Si (MONOS) structures. For MONOS devices, SiO"2 tunnel layers were formed on poly-Si channels using thermal oxidation, radical oxidation, and LP-CVD. We investigated the characteristics of each SiO"2 tunnel layer on poly-Si including breakdown, leakage current and FN tunneling. Radical SiO"2 and LP-TEOS SiO"2 showed larger breakdown voltages with more uniform thickness than thermal SiO"2 on poly-Si channels. MONOS devices with radical SiO"2 and LP-TEOS SiO"2 tunnel layers showed improved program/erase (P/E) and endurance compared with thermal SiO"2. In particular, the MONOS device with LP-TEOS SiO"2 showed the largest memory window with the fastest P/E operation, which was attributed to enhanced defect-assisted tunneling in LP-TEOS SiO"2. The endurances of MONOS devices were measured and related to the flat-band voltage shift in conjunction with trapped charge types in SiO"2 tunnel dielectrics.