Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Relaxing non-volatility for fast and energy-efficient STT-RAM caches
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
Multi retention level STT-RAM cache designs with a dynamic refresh scheme
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
TapeCache: a high density, energy efficient cache based on domain wall memory
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
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The racetrack memory technology utilizes magnetic domains along a nanoscopic wire to obtain ultra-high data storage density. The recent success in the planar racetrack nanowire promised its fabrication feasibility and future scalability, bringing more design challenges and opportunities. In this paper, we initialize the optimization of racetrack memory embracing design considerations across multiple layers, including cell design, array structure, architecture organization, and data management. Our evaluation shows that racetrack memory based cache can achieve 6.4x area reduction, 25% performance enhancement, and 62% energy saving, compared to STT-RAM cache design. The benefit over SRAM technology is even more significant.