Handling long-latency loads in a simultaneous multithreading processor
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the 45th annual Design Automation Conference
Hybrid cache architecture with disparate memory technologies
Proceedings of the 36th annual international symposium on Computer architecture
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing
Proceedings of the 46th Annual Design Automation Conference
Characterizing flash memory: anomalies, observations, and applications
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Energy reduction for STT-RAM using early write termination
Proceedings of the 2009 International Conference on Computer-Aided Design
Relaxing non-volatility for fast and energy-efficient STT-RAM caches
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
Processor caches with multi-level spin-transfer torque ram cells
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Motorola Xoom: The Missing Manual
Motorola Xoom: The Missing Manual
Unleashing the potential of MLC STT-RAM caches
Proceedings of the International Conference on Computer-Aided Design
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MLC STT-MRAM (Multi-level Cell Spin-Transfer Torque Magnetic RAM), an emerging non-volatile memory technology, has become a promising candidate to construct L2 caches for high-end embedded processors. However, the long write latency limits the effectiveness of MLC STT-MRAM based L2 caches. In this paper, we address this limitation with two novel designs: Line Pairing (LP) and Line Swapping (LS). LP forms fast cachelines by re-organizing MLC soft bits which are faster to write. LS dynamically stores frequently written data into these fast cachelines. Our experimental results show that LP and LS improve system performance by 15% and reduce energy consumption by 21%.