Fault-Tolerance Through Scheduling of Aperiodic Tasks in Hard Real-Time Multiprocessor Systems
IEEE Transactions on Parallel and Distributed Systems
Fast and Precise WCET Prediction by Separated Cache andPath Analyses
Real-Time Systems - Special issue on worst-case execution-time analysis
Timing Analysis for Instruction Caches
Real-Time Systems - Special issue on worst-case execution-time analysis
Analysis of Checkpointing for Real-Time Systems
Real-Time Systems
On Predicting Data Cache Behavior for Real-Time Systems
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
RTCSA '99 Proceedings of the Sixth International Conference on Real-Time Computing Systems and Applications
A Modular & Retargetable Framework for Tree-Based WCET Analysis
ECRTS '01 Proceedings of the 13th Euromicro Conference on Real-Time Systems
Modeling out-of-order processors for WCET analysis
Real-Time Systems
Timing predictability of cache replacement policies
Real-Time Systems
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches
RTSS '08 Proceedings of the 2008 Real-Time Systems Symposium
Circuit techniques for dynamic variation tolerance
Proceedings of the 46th Annual Design Automation Conference
A resilience roadmap: (invited paper)
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
PROARTIS: Probabilistically Analyzable Real-Time Systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
A cache design for probabilistically analysable real-time systems
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
Semiconductor technology evolution suggests that permanent failure rates will increase dramatically with scaling, in particular for SRAM cells. While well known approaches such as error correcting codes exist to recover from failures and provide fault-free chips, they will not be affordable anymore in the future due to their non-scalable cost. Consequently, other approaches like fine grain disabling and reconfiguration of hardware elements (e.g. individual functional units or cache blocks) will become economically necessary. This fine-grain disabling will lead to degraded performance compared to a fault-free execution. To the best of our knowledge, all static worst-case execution time (WCET) estimation methods assume fault-free architectures. Their result is not safe anymore when using fine grain disabling of hardware components, which degrades performance. In this paper we provide the first method that statically calculates a probabilistic WCET bound in the presence of permanent faults in instruction caches. The proposed method, from a given program, cache configuration and probability of cell failure, derives a probabilistic WCET bound. The proposed method, because it relies on static analysis, is guaranteed to identify the longest program path, its probabilistic nature only stemming from the presence of faults. The method is computationally tractable because it does not require an exhaustive enumeration of the possible locations of faulty cache blocks. Experimental results show that it provides WCET estimates very close to, but never below, the method that derives probabilistic WCETs by enumerating all possible locations of faulty cache blocks. The proposed method not only allows to quantify the impact of permanent faults on WCET estimates, but also can be used in architectural exploration frameworks to select the most appropriate fault management mechanisms.