Multiprocessor cache synchronization: issues, innovations, evolution
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
High performance integrated Prolog processor IPP
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
RISCs vs. CISCs for Prolog: a case study
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Memory performance of prolog architectures
Memory performance of prolog architectures
Computing with logic: logic programming with Prolog
Computing with logic: logic programming with Prolog
Tradeoffs in processor-architecture and data-buffer design
Tradeoffs in processor-architecture and data-buffer design
A very fast prolog compiler on multiple architectures
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
Performance studies of a Prolog machine architecture
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Design of a high-speed Prolog machine (HPM)
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
Register allocation for free: The C machine stack cache
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
RISC I: A Reduced Instruction Set VLSI Computer
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
A Prolog Compiler for the PLM
Comparative analysis of computer architectures
Comparative analysis of computer architectures
Reduced instruction set computer architectures for vlsi (microprocessor, risc, multiple-windows - of - registers)
Design and performance of a coherent cache for parallel logic programming architectures
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Evaluation of memory system for integrated Prolog processor IPP
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
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Several local data buffers are proposed and measurements are presented for variations of the Warren Abstract Machine (WAM) architecture for Prolog. Choice point buffers, stack buffers, split-stack buffers, multiple register sets, copyback caches, and “smart” caches are examined. Statistics collected from four benchmark programs indicate that small conventional local memories perform quite well because of the WAM's high locality. The data memory performance results are equally valid for native code and reduced instruction set implementations of Prolog.