Design and performance of a coherent cache for parallel logic programming architectures

Authors:
A. Goto;A. Matsumoto;E. Tick
Affiliations:
Institute for New Generation Computer Technology (ECOT);Mitsubishi Electric Corporation, MIEL, 5-l-l Ofuna, Kamakura-city, Kanagawa;University of Tokyo, RCAST, 4-61 Komaba, Megurcku, Tokyo
Venue:
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Year:
1989

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Abstract

This paper describes the design and performance of a tightly-coupled shared-memory coherent cache optimized for the execution of parallel logic programming architectures. The cache utilizes a copy-back write-allocation protocol having five states and a hardware lock mechanism. Optimizations for logic programming are introduced in four software-controlled memory access commands: direct-write, exclusive-read, read-purge, and read-invalidate. In this paper we describe these operations and present simulated measurements showing their performance advantage for an architecture of the committed-choice language KL1. The cache optimizations also improve the performance of non-committed-choice languages, such as OR-parallel Prolog. A version of the cache design described here is currently being implemented for ICOT's Parallel Inference Machine (PIM).