Programming in Prolog (2nd ed.)
Programming in Prolog (2nd ed.)
The 5th Conference on Logic programming '86
Performance studies of a Prolog machine architecture
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Design of a high-speed Prolog machine (HPM)
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Architecture of high performance integrated Prolog processor IPP
ACM '87 Proceedings of the 1987 Fall Joint Computer Conference on Exploring technology: today and tomorrow
Data buffer performance for sequential Prolog architectures
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Evaluation of memory system for integrated Prolog processor IPP
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Design and performance measurements of a parallel machine for the unification algorithm
MICRO 22 Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture
A Parallel Unification Machine
IEEE Micro
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To realize the highest performance possible for a sequential processor, and to realize utilization of a large amount of existing software, an integrated Prolog processor (IPP) and its optimized compiler are now being developed.A tagged architecture under constraints of a general purpose computer and a memory management strategy to achieve a high performance are discussed and then an IPP architecture is presented. Based on the Prolog instruction set, which is an extension of Warren's, the Prolog compiler introduces new functions such as indexing by the optimal argument and global register assignment across determinate built-in predicates.The performance of the IPP for the append program is 1 million logical inferences per second, which is the highest possible for a sequential processor. In the 8-queen program a considerable speed-up is obtained by the new functions.