Design and performance measurements of a parallel machine for the unification algorithm

Authors:
F. N. Sibai;L. Watson;M. Lu
Affiliations:
Department of Electrical Engineering, Texas A&M University, College Station, Texas;Department of Electrical Engineering, Texas A&M University, College Station, Texas;Department of Electrical Engineering, Texas A&M University, College Station, Texas
Venue:
MICRO 22 Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture
Year:
1989

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Abstract

Unification is known to be the most repeated operation in logic programming and PROLOG interpreters. To speed up the execution of logic programs, the performance of unification must be improved. We propose a parallel unification machine for speeding up the unification algorithm. The machine is simulated at the register transfer level and the simulation results as well as performance comparison with a serial unification coprocessor are presented.