Principles of artificial intelligence
Principles of artificial intelligence
Performance studies of a Prolog machine architecture
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
A hardware unification unit: design and analysis
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Design and performance measurements of a parallel machine for the unification algorithm
MICRO 22 Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture
Pipelined OR-parallelism architecture for parallel execution of Prolog
IEA/AIE '90 Proceedings of the 3rd international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 2
A Parallel Unification Machine
IEEE Micro
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This paper describes the architecture and the current implementation of the hardware unification unit (HUU). The HUU performs the literal unification operation in Prolog processing. It is designed as a coprocessor to a host system that handles other operations of Prolog processing such as bookkeeping and sequencing. After the host system provides input values to the HUU and activates it, the HUU works independently from the host system; when it finishes its operation it reports the result to the host system. The HUU contains local memory that stores the variable binding information. The microinstructions and a sample microprogram of the HUU are described. Performance measures obtained from the HUU simulator are presented and discussed.