On the sequential nature of unification
Journal of Logic Programming
A unification processor based on a uniformly structured cellular hardware
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
The architecture of the hardware unification unit and an implementation
MICRO 18 Proceedings of the 18th annual workshop on Microprogramming
High performance integrated Prolog processor IPP
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Programming in Prolog
A Machine-Oriented Logic Based on the Resolution Principle
Journal of the ACM (JACM)
A hardware unification unit: design and analysis
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
An Efficient Unification Algorithm
ACM Transactions on Programming Languages and Systems (TOPLAS)
Efficient reordering of C-PROLOG
CSC '93 Proceedings of the 1993 ACM conference on Computer science
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A parallel unification machine (PUM) that speeds up the unification algorithm is proposed. The PUM partitions unification into a match step and a consistency-check step, conducts these two steps concurrently, and takes advantage of the match parallelism. The machine architecture, algorithms, data formats, and processor organization are described. The machine has been simulated at the register-transfer level with the ISPS computer description language. The simulated performance is compared with that of two serial unification coprocessors. Significant speedup is observed.