Architecture of high performance integrated Prolog processor IPP

Authors:
S. Yamaguchi;T. Bandoh;K. Kurosawa;M. Morioka
Affiliations:
Hitachi Research Laboratory, Hitachi, Ltd, 4026, Kuji, Hitachi, Japan;Hitachi Research Laboratory, Hitachi, Ltd, 4026, Kuji, Hitachi, Japan;Hitachi Research Laboratory, Hitachi, Ltd, 4026, Kuji, Hitachi, Japan;Hitachi Research Laboratory, Hitachi, Ltd, 4026, Kuji, Hitachi, Japan
Venue:
ACM '87 Proceedings of the 1987 Fall Joint Computer Conference on Exploring technology: today and tomorrow
Year:
1987

Citing 3
Cited 1

High performance integrated Prolog processor IPP

ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Programming in Prolog

Programming in Prolog
Design of a high-speed Prolog machine (HPM)

ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture

Evaluation of memory system for integrated Prolog processor IPP

ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper describes a high speed integrated Prolog processor (IPP) which integrates the extended Warren's Prolog instructions, and its acceleration hardware into a 32-bit super-minicomputer. Tagged data format and instruction format under constraints of a general purpose machine architecture, and aspects of the hardware architecture of the IPP which includes some special hardware for an accelerating Prolog instruction execution are described.The IPP is implemented by high speed ECL(emitter coupled logic) gate arrays and its inference performance is 1 MLIPS for the deterministic concatenate program.It is easy for the IPP to link Prolog programs and existing procedural programs. And it can share its hardware resource with a base machine. Therefore, using the IPP, a high cost/performance practical AI system can be realized.