M68000: 16/32-bit microprocessor: programmer's reference manual (4th ed.)
M68000: 16/32-bit microprocessor: programmer's reference manual (4th ed.)
High-speed top-of-stack scheme for VLSI processor: a management algorithm and its analysis
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Analyzing multiple register sets
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Dhrystone: a synthetic systems programming benchmark
Communications of the ACM
Computer Architecture: A Structured Approach
Computer Architecture: A Structured Approach
Register allocation for free: The C machine stack cache
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
Performance evaluation of on-chip register and cache organizations
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
FLIP-FLOP: a stack-oriented multiprocessing system
SPAA '90 Proceedings of the second annual ACM symposium on Parallel algorithms and architectures
FLIP-FLOP: a stack-oriented multiprocessing system
ACM SIGARCH Computer Architecture News - Symposium on parallel algorithms and architectures
An integrated memory management scheme for dynamic alias resolution
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
FLIP-FLOP: a stack-oriented multiprocessing system
ACM SIGFORTH Newsletter - Special issue: Hardware
CONS should not CONS its arguments, or, a lazy alloc is a smart alloc
ACM SIGPLAN Notices
Decoupling local variable accesses in a wide-issue superscalar processor
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Optimization strategies of stack control
PPPJ '02/IRE '02 Proceedings of the inaugural conference on the Principles and Practice of programming, 2002 and Proceedings of the second workshop on Intermediate representation engineering for virtual machines, 2002
Study of a Non-Markovian Stack Management Model in a Two-Level Memory
Programming and Computing Software
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In this paper, the feasibility of using register banks as a top of stack (TOS) buffer is demonstrated. A quantitative performance evaluation is made of three automatic TOS buffer management algorithms: a simple single pointer algorithm, an intelligent single pointer algorithm, and a sophisticated double pointer algorithm. An automatically managed TOS buffer can effectively cache local data accesses resulting in a large memory traffic reduction. Results demonstrate that a small (with respect to the size of the benchmark data set) TOS buffer provides a very high data reference hit ratio and requires minimal processor intervention for TOS buffer management. The simple single pointer algorithm is shown to provide the best overall performance for various metrics including memory bandwidth, TOS buffer hit ratio, processor intervention, and processor execution speed.