Cache memories: A tutorial and survey of current research directions

Authors:
Robert P. Cook;Cathy J. Linn;Joseph L. Linn;Terry M. Walker
Affiliations:
-;-;-;-
Venue:
ACM '82 Proceedings of the ACM '82 conference
Year:
1982

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Abstract

The tutorial presents a unified nomenclature for the description of cache memory systems. Using this foundation, examples of existing cache memory systems are detailed and compared. The second presentation discusses a programmable cache memory architecture. In this architecture, intelligence is added to the cache to direct the activity between the cache and the main memory. Also to be described are heuristics for programming the cache which allow the additional power to be exploited. The third presentation deals with innovations involving systems where the cache memory is not used as a simple high speed buffer for main memory. A straight forward example of this appears in IBM's Translation Lookaside Buffer on 370s with dynamic address translation hardware. Other examples are to be described include a cache system for the activation stack of a block structured language, a cache system to store subexpressions for an expression oriented architecture, and a multiprocessor architecture that relies on two levels of cache.