Organization and VLSI implementation of MIPS
Advances in VLSI and Computer Systems
Computer
Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
Analyzing multiple register sets
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
A reduced register file for RISC architectures
ACM SIGARCH Computer Architecture News
Register allocation for free: The C machine stack cache
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
Architecture of SOAR: Smalltalk on a RISC
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Reduced instruction set computer architectures for vlsi (microprocessor, risc, multiple-windows - of - registers)
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The issues involved in designing multiple-register window schemes are examined, and fixed-size, variable-size and two-size window organizations are discussed. These three multiple-register approaches are compared. A detailed example is presented, showing that the proposed two-size register window scheme has significant advantages over both fixed-size and variable-size schemes. A prototype design is presented.