Smalltalk-80: the language and its implementation
Smalltalk-80: the language and its implementation
Efficient implementation of the smalltalk-80 system
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Architecture of a VLSI instruction cache for a RISC
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RISC I: A Reduced Instruction Set VLSI Computer
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A symbolic design system for integrated circuits
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An electronic circuit cad framework (vlsi, graphics, geometry)
An electronic circuit cad framework (vlsi, graphics, geometry)
Register allocation in the SPUR Lisp compiler
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Survey on special purpose computer architectures for AI
ACM SIGART Bulletin
Microprogrammable processor for object-oriented architecture
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Fast object-oriented procedure calls: lessons from the Intel 432
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
An in-cache address translation mechanism
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
SOAR: Smalltalk without bytecodes
OOPLSA '86 Conference proceedings on Object-oriented programming systems, languages and applications
Swamp: a fast processor for Smalltalk-80
OOPLSA '86 Conference proceedings on Object-oriented programming systems, languages and applications
Virtual instruments: object-oriented program synthesis
OOPLSA '86 Conference proceedings on Object-oriented programming systems, languages and applications
Design of a distributed object manager for the Smalltalk-80 system
OOPLSA '86 Conference proceedings on Object-oriented programming systems, languages and applications
Compiling Smalltalk-80 to a RISC
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
RISCs vs. CISCs for Prolog: a case study
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
A simple interprocedural register allocation algorithm and its effectiveness for LISP
ACM Transactions on Programming Languages and Systems (TOPLAS)
Architectural support for reduced register saving/restoring in single-window register files
ACM Transactions on Computer Systems (TOCS)
The architecture of a memory management unit for object-oriented systems
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A Parallel Virtual Machine for Programs Composed of Abstract Data Types
IEEE Transactions on Computers
Performance of a hardware-assisted real-time garbage collector
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Reduced instruction set computers
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Execution characteristics of desktop applications on Windows NT
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PLA driver selection: an analytic approach
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
The implementation of PC Scheme
LFP '86 Proceedings of the 1986 ACM conference on LISP and functional programming
Highlight of VLSI at research Berkeley
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
Do Object-Oriented Languages Need Special Hardware Support?
ECOOP '95 Proceedings of the 9th European Conference on Object-Oriented Programming
DAC '84 Proceedings of the 21st Design Automation Conference
Generation Scavenging: A non-disruptive high performance storage reclamation algorithm
SDE 1 Proceedings of the first ACM SIGSOFT/SIGPLAN software engineering symposium on Practical software development environments
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Proceedings of the 2007 ACM symposium on Applied computing
A self-maintained memory module supporting DMM
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Overview of garbage collection in symbolic computing
ACM SIGPLAN Lisp Pointers
And then there were none: a stall-free real-time garbage collector for reconfigurable hardware
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ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
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Smalltalk on a RISC (SOAR) is a simple, Von Neumann computer that is designed to execute the Smalltalk-80 system much faster than existing VLSI microcomputers. The Smalltalk-80 system is a highly productive programming environment but poses tough challenges for implementors: dynamic data typing, a high level instruction set, frequent and expensive procedure calls, and object-oriented storage management. SOAR compiles programs to a low level, efficient instruction set. Parallel tag checks permit high performance for the simple common cases and cause traps to software routines for the complex cases. Parallel register initialization and multiple on-chip register windows speed procedure calls. Sophisticated software techniques relieve the hardware of the burden of managing objects. We have initial evaluations of the effectiveness of the SOAR architecture by compiling and simulating benchmarks, and will prove SOAR's feasibility by fabricating a 35,000-transistor SOAR chip. These early results suggest that a Reduced Instruction Set Computer can provide high performance in an exploratory programming environment.