Smalltalk-80: the language and its implementation
Smalltalk-80: the language and its implementation
Architecture of the Symbolics 3600
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
A real-time garbage collector based on the lifetimes of objects
Communications of the ACM
Efficient implementation of the smalltalk-80 system
POPL '84 Proceedings of the 11th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
A retrospective on the Dorado, a high-performance personal computer
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Architecture of SOAR: Smalltalk on a RISC
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
The Design and Evaluation of A High Performance Smalltalk System
The Design and Evaluation of A High Performance Smalltalk System
SOAR: Smalltalk without bytecodes
OOPLSA '86 Conference proceedings on Object-oriented programming systems, languages and applications
Parallelizing a database programming language
DPDS '88 Proceedings of the first international symposium on Databases in parallel and distributed systems
The architecture of a memory management unit for object-oriented systems
ACM SIGARCH Computer Architecture News
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A processor for the Smalltalk-80↑ programming language is described. This machine is implemented using a standard bit slice ALU and sequencer, TTL MSI, and NMOS LSI RAMS. It executes an instruction set similar to the Smalltalk-80 virtual machine instruction set. The data paths of the machine are optimized for rapid Smalltalk-80 execution by the inclusion of a context cache, tag checking, and a hardware method cache. Each context is only partly initialized when created, and has no memory allocated for it until a possibly non-LIFO reference to it is created. The machine is microprogrammed, and uses a simple next micro-address prediction strategy to obtain most of the performance of pipelining without the attendant complexity. The machine can execute simple instructions at over 7M bytecodes per second and has a predicted average throughput of 1.9M bytecodes per second.A processor for the Smalltalk-80↑ programming language is described. This machine is implemented using a standard bit slice ALU and sequencer, TTL MSI, and NMOS LSI RAMS. It executes an instruction set similar to the Smalltalk-80 virtual machine instruction set. The data paths of the machine are optimized for rapid Smalltalk-80 execution by the inclusion of a context cache, tag checking, and a hardware method cache. Each context is only partly initialized when created, and has no memory allocated for it until a possibly non-LIFO reference to it is created. The machine is microprogrammed, and uses a simple next micro-address prediction strategy to obtain most of the performance of pipelining without the attendant complexity. The machine can execute simple instructions at over 7M bytecodes per second and has a predicted average throughput of 1.9M bytecodes per second.