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ACM SIGARCH Computer Architecture News
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The author describes MUTABOR, a micro-programmable coprocessor that works with a 68020 CPU to control and update a 4096-entry address translation cache that achieves an excellent hit rate. He defines the requirements for an object-oriented memory-management unit, and outlines the architecture of MUTABOR and the object-addressing mechanism. He also discusses the design decisions concerning the address translation cache, which were based on simulation results.