Empirical evaluation of some features of instruction set processor architectures
Communications of the ACM
Implications of structured programming for machine architecture
Communications of the ACM
Compiler Construction for Digital Computers
Compiler Construction for Digital Computers
More data on the O/W ratios: a note on a paper by Flynn
ACM SIGARCH Computer Architecture News
More on microprocessors of the future
ACM SIGARCH Computer Architecture News
Performance evaluation of multiple register sets
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Register allocation for free: The C machine stack cache
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
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Register allocation schemes are presented that effectively use many registers in the execution of block-structured languages. Simulation statistics for a machine with many registers and a conventional architecture are compared. The results indicate that the average operand access time and the required memory bandwidth of conventional machines can be significantly reduced. The implications of the register allocation schemes for machine architecture are discussed.