Computer programming and architecture: The VAX
Computer programming and architecture: The VAX
Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
Analyzing multiple register sets
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
A reduced register file for RISC architectures
ACM SIGARCH Computer Architecture News
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
An architecture with many operand registers to efficiently execute block-structured languages
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Exploiting parallel microprocessor microarchitectures with a compiler code generator
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Performance evaluation of on-chip register and cache organizations
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Register relocation: flexible contexts for multithreading
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
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In this paper a DEC VAX with multiple register sets is evaluated under many differently sized register sets. Both the number of register sets and the number of registers per set were varied. Performance, measured in terms of memory traffic, is compared to that of a standard VAX. Memory traffic is measured from many real program traces on the standard processor and from transformations of the trace for the multiple register set processors. Results are presented for each program; an empirical formula is derived which describes the average program's behavior. A decrease in memory references of approximately 16% can be expected using multiple register sets.