A class of compatible cache consistency protocols and their support by the IEEE futurebus
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
At work or play, he's the captain
IEEE Spectrum
CLIPPER 32-bit microprocessor: user's manual
CLIPPER 32-bit microprocessor: user's manual
Computer programming and architecture: The VAX
Computer programming and architecture: The VAX
Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
ACM Computing Surveys (CSUR)
Dhrystone: a synthetic systems programming benchmark
Communications of the ACM
Communications of the ACM
MC 68000 16-Bit Microprocessor User's Manual
MC 68000 16-Bit Microprocessor User's Manual
Digital Computer Arithmetic
A performance evaluation of the Intel iAPX 432
ACM SIGARCH Computer Architecture News
Measurement and analysis of instruction use in the VAX-11/780
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Hardware/software tradeoffs for increased performance
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
A case study of VAX-11 instruction set usage for compiler execution
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
A Characterization of Processor Performance in the vax-11/780
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
An instruction timing model of CPU performance
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Problems, Directions and Issues in Memory Hierarchy
Problems, Directions and Issues in Memory Hierarchy
The Memory Architecture and the Cache and Memory Management Unit for
The Memory Architecture and the Cache and Memory Management Unit for
Efficient (stack) algorithms for analysis of write-back and sector memories
ACM Transactions on Computer Systems (TOCS)
CPU Cache Prefetching: Timing Evaluation of Hardware Implementations
IEEE Transactions on Computers
A Comparison of RISC Architectures
IEEE Micro
Branch Target Buffer Design and Optimization
IEEE Transactions on Computers
EURO-DAC '90 Proceedings of the conference on European design automation
International Journal of Applied Logistics
Hi-index | 48.22 |
Intergraph's CLIPPER microprocessor is a high performance, three chip module that implements a new instruction set architecture designed for convenient programmability, broad functionality, and easy future expansion.