Line (block) size choice for CPU cache memories
IEEE Transactions on Computers
Cache performance of operating system and multiprogramming workloads
ACM Transactions on Computer Systems (TOCS)
Efficient (stack) algorithms for analysis of write-back and sector memories
ACM Transactions on Computer Systems (TOCS)
The Clipper processor: instruction set architecture and implementation
Communications of the ACM
Improving Quicksort Performance with a Codeword Data Structure
IEEE Transactions on Software Engineering
Evaluating Associativity in CPU Caches
IEEE Transactions on Computers
CPU Cache Prefetching: Timing Evaluation of Hardware Implementations
IEEE Transactions on Computers
The performance impact of block sizes and fetch strategies
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Power consumption and reduction in a real, commercial multimedia core
Proceedings of the 6th ACM conference on Computing frontiers
Hi-index | 0.02 |
The Fairchild CLIPPER is a new high-performance three chip module consisting of a microprocessor chip and two cache and memory management (CAMMU) chips, mounted on a small PC board. CLIPPER implements anew instruction set architecture which has been designed for high performance, convenient programmability, broad functionality and sufficient architectural "openness" to permit future evolution and a variety of implementations. The CLIPPER memory architecture is a separate 32 bit logical address space for each of the user and supervisor, with facilities for transferring information from one to the other. Virtual memory support is provided by a memory management unit on each CAMMU, each of which includes a translator that maps 32-bit virtual addresses through a two level page table to 4096 byte pages, and a 2-way set associative with 16-byte lines and with LRU replacement within each set. The caching policy (write-through, copy back, non-cacheable) may be specified on a page basis, as may the protection modes (read, write, execute, by user and supervisor). The bus protocol and interface provides a mechanism to maintain cache consistency when the bus is shared by multiple processors and I/O devices with overlapping physical address spaces. There is a translator, cache and TLB implemented on each of the two CAMMU (cache and memory management unit) chips. In this paper, we discuss, in some detail, the memory architecture and the cache and memory management units of the Fairchild CLIPPER. Timing for operations and performance estimated are provided. There is some discussion as well for the various implementation decisions and the tradeoffs involved.