The Clipper processor: instruction set architecture and implementation
Communications of the ACM
Available instruction-level parallelism for superscalar and superpipelined machines
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
IEEE Transactions on Computers
Super-Scalar Processor Design
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A description is given of the C400, the first complete redesign of the Clipper reduced instruction-set computing architecture since its introduction in 1985. The C400 delivers three times the performance of the C300, yet retains full-code compatibility with earlier Clippers. The C400 combines two architectural approaches to attain its performance goals. The first approach, superscalar operation, allows the processor to begin the execution of more than one instruction during each clock cycle. The C400, which is moderately superscalar, can dispatch two instructions per clock cycle. The C400 also embodies the design concept of superpipelining, an approach that emphasizes high clock rates and deep execution pipelines in attaining high computational performance. The discussion covers the programming model, early hardware implementations, the C400 project goals and approaches, C400 performance, the integer unit design, the load/store pipeline, the floating-point unit design, the superscalar/superpipelined architecture, circuit design, and the advantages of the multichip implementation.