Experience with processes and monitors in Mesa
Communications of the ACM
Implications of structured programming for machine architecture
Communications of the ACM
Communications of the ACM
On the transfer of control between contexts
Programming Symposium, Proceedings Colloque sur la Programmation
An overview of the mesa processor architecture
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
Empirical analysis of the mesa instruction set
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
Computer instruction set usage by programmers: an empirical investigation
Communications of the ACM
ACM SIGARCH Computer Architecture News
The design and development of a dynamic program behavior measurement tool for the Intel 8086/88
ACM SIGARCH Computer Architecture News
An analysis of MIPS and SPARC instruction set utilization on the SPEC benchmarks
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Solutions Relating Static and Dynamic Machine Code Measurements
IEEE Transactions on Computers
Performance of the VAX-11/780 translation buffer: simulation and measurement
ACM Transactions on Computer Systems (TOCS)
A characterization of processor performance in the VAX-11/780
25 years of the international symposia on Computer architecture (selected papers)
LISP on a reduced-instruction-set-processor
LFP '86 Proceedings of the 1986 ACM conference on LISP and functional programming
Dhrystone: a synthetic systems programming benchmark
Communications of the ACM
A performance evaluation of the Intel iAPX 432
ACM SIGARCH Computer Architecture News
Incorporating compiler feedback into the design of ASIPs
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Measurement and analysis of instruction use in the VAX-11/780
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Integrated program measurement and documentation tools
ICSE '84 Proceedings of the 7th international conference on Software engineering
A Characterization of Processor Performance in the vax-11/780
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
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The Mesa architecture is implemented on a variety of processors, and dynamic instruction frequency data for two programs is used to analyze the architecture in an implementation independent fashion. The Mesa compiler allocates variables in an order based upon their static frequency of use, and measurements are provided that show that these static predictions predict run time usage as well. We provide an evaluation of the advantages and costs of Mesa's compact byte encoding, its reliance upon an evaluation stack, and its use of memory. The Mesa language has evolved over time in a hardware environment oriented around 16-bit quantities with growing use of and accommodations to 32-bit quantities. The cost of emulating 32-bit data paths on a 16-bit machine is identified for a program that heavily exploits longer values. Several potential areas for improving the execution speed of a Mesa processor with special purpose hardware are identified.