C language algorithms for digital signal processing
C language algorithms for digital signal processing
High level synthesis of pipelined instruction set processors and back-end compilers
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Instruction set definition and instruction selection for ASIPs
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
An analysis of a mesa instruction set using dynamic instruction frequencies
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
Using compilers for heterogeneous system design
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
Methodical Low-Power ASIP Design Space Exploration
Journal of VLSI Signal Processing Systems
Rapid Configuration and Instruction Selection for an ASIP: A Case Study
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Instruction set synthesis with efficient instruction encoding for configurable processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper presents a framework for providing feedback from an optimizing compiler into the design of an ASIP (Application Specific Instruction-set Processor). The optimizing compiler is used to assess the hardware needs of a suite of applications to which the ASIP is to be tuned. By incorporating the compiler into the design process, the design space is increased as more information is provided at an earlier stage during the design process. Our initial study involves detecting potentially chainable operation sequences using scheduling techniques developed for exploiting instruction-level parallelism. Results of this study are included.