Microprogramming heritage of RISC design

Authors:
Liwen Shih
Affiliations:
Computer System Design & Engineering, University of Houston - Clear Lake, Houston, Texas
Venue:
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Year:
1990

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Abstract

Technology impact brings Reduced Instruction Set Computer (RISC) design approach back to the stage of computer architecture evolution. While RISC architecture grab attention by their flying instruction rates, this paper summarizes the current design of micro-architectures and analyzes the tradeoffs between RISC approach and Microprogramming approach especially on the vertical migration among hardware, firmware, compilation and software. RISCs' simplicity is contrasted by the regularity of microprogrammed control. The RISC design incentives are categorized into three perspectives, namely, technology-driven, application-driven, and performance-driven. Traditional firmware migration approaches are reviewed and related to RISC design philosophy as well as Writable Instruction Set Computer (WISC) concept. Research such as Firmware Migration candidates selection can be applied to RISC instruction set design. Similarly, micro-code generation and compaction research can be used to construct the smart, optimizing RISC compiler. Horizontal microcode approach is interpreted as the Very Long Instruction Word (VLIW) architecture. Incorporating in the discussion about new design trends affected by GaAs, memory technology, and super-computing a clue for the direction of future-proof micro-architecture and microprogramming is projected.