Global register allocation at link time
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Branch folding in the CRISP microprocessor: reducing branch delay to zero
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
The hardware architecture of the CRISP microprocessor
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
Postpass Code Optimization of Pipeline Constraints
ACM Transactions on Programming Languages and Systems (TOPLAS)
An analysis of inline substitution for a structured programming language
Communications of the ACM
The effect of instruction fetch strategies upon the performance of pipelined instruction units
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Ease: An Environment for Architecture Study and Experimentation
Ease: An Environment for Architecture Study and Experimentation
Methods for Saving and Restoring Register Valves across Function Calls
Methods for Saving and Restoring Register Valves across Function Calls
SPIRE: streaming processing with instructions release element
ACM SIGARCH Computer Architecture News
Toward zero-cost branches using instruction registers
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Reducing indirect function call overhead in C++ programs
POPL '94 Proceedings of the 21st ACM SIGPLAN-SIGACT symposium on Principles of programming languages
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In an attempt to reduce the number of operand memory references, many RISC machines have thirty-two or more general-purpose registers (e.g., MIPS, ARM, Spectrum, 88K). Without special compiler optimizations, such as inlining or interprocedural register allocation, it is rare that a compiler will use a majority of these registers for a function. This paper explores the possibility of using some of these registers to hold branch target addresses and the corresponding instruction at each branch target. To evaluate the effectiveness of this scheme, two machines were designed and emulated. One machine had thirty-two general-purpose registers used for data references, while the other machine had sixteen data registers and sixteen registers used for branching. The results show that using registers for branching can effectively reduce the cost of transfers of control.