Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Reasoning About Time in Higher-Level Language Software
IEEE Transactions on Software Engineering
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Crafting a compiler with C
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
An architecture for software-controlled data prefetching
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
MIPS RISC architectures
Reducing memory latency via non-blocking and prefetching caches
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
ACM Computing Surveys (CSUR)
The effect of instruction fetch strategies upon the performance of pipelined instruction units
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Aspects of cache memory and instruction buffer performance
Aspects of cache memory and instruction buffer performance
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Cache memories have been extensively used to bridge the speed gap betweenhigh speed processors and relatively slow main memory. However, they are notwidely used in real-time systems due to their unpredictable performance. Thispaper proposes an instruction prefetching scheme called threaded prefetchingas an alternative to instruction caching in real-time systems. In theproposed threaded prefetching, an instruction block pointer called a threadis assigned to each instruction memory block and is made to point to the nextblock on the worst case execution path that is determined by a compile-timeanalysis. Also, the thread is not updated throughout the entire programexecution to guarantee predictability. This paper also compares the worstcase performances of various previous instruction prefetching schemes withthat of the proposed threaded prefetching. By analyzing several benchmarkprograms, we show that the worst case performance of the proposed scheme issignificantly better than those of previous instruction prefetching schemes.The results also show that when the block size is large enough the worst caseperformance of the proposed threaded prefetching scheme is almost as good asthat of an instruction cache with 100 % hit ratio.