Digital Image Restoration
IEEE Transactions on Computers
A production implementation of an associative array processor: STARAN
AFIPS '72 (Fall, part I) Proceedings of the December 5-7, 1972, fall joint computer conference, part I
A Pipelined Pseudoparallel System Architecture for Real-Time Dynamic Scene Analysis
IEEE Transactions on Computers
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Two-dimensional arrays of microprocessors are considered for the implementation of image processors that are formulated according to a certain state-space model. The microprocessors are totally synchronized operating with the same clock and executing the same instructions, communicating with each other through local memory units. This allows the use of such an array as a pipeline for the processing of successive images or sections of one image, to achieve a relatively fast effective speed.