Data-Driven and Demand-Driven Computer Architecture
ACM Computing Surveys (CSUR)
A pipelined pseudoparallel system architecture for motion analysis
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
A microprocessor-controlled asynchronous circuit switching network
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Two-Dimensional Microprocessor Pipelines for Image Processing
IEEE Transactions on Computers
Construction of a Generalized Connector with 5.8 n log2n Edges
IEEE Transactions on Computers
PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition
IEEE Transactions on Computers
Communication Issues in the Design and Analysis of Parallel Algorithms
IEEE Transactions on Software Engineering
Software Design Representation Using Abstract Process Networks
IEEE Transactions on Software Engineering
Performance Evaluation of Asynchronous Concurrent Systems Using Petri Nets
IEEE Transactions on Software Engineering
Imprecision in Computer Vision
Computer
Pluribus: a reliable multiprocessor
AFIPS '75 Proceedings of the May 19-22, 1975, national computer conference and exposition
Design of software for distributed/multiprocessor systems
AFIPS '82 Proceedings of the June 7-10, 1982, national computer conference
Graph Theoretical Analysis and Design of Multistage Interconnection Networks
IEEE Transactions on Computers
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In this paper we introduce the concept of pseudoparallelism, in which the serial algorithm is partitioned into several noninteractive independent subtasks so that parallelism can be used within each subtask level. This approach is illustrated by applying it to a real-time dynamic scene analysis. Complete details of such a pseudoparallel architecture with an emphasis to avoid interprocessor communications have been worked out. Problems encountered in the course of designing such a system with a distributed operating system (no master control) have been outlined and necessary justifications have been provided. A scheme indicating various memory modules, processing elements, and their data-path requirements is included and ways to provide continuous flow of partitioned information in the form of a synchronized pipeline are described.