Study of multistage SIMD interconnection networks
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
Graph theoretic approach to multistage interconnection networks
Graph theoretic approach to multistage interconnection networks
Notes on Shuffle/Exchange-Type Switching Networks
IEEE Transactions on Computers
Data Manipulating Functions in Parallel Processors and Their Implementations
IEEE Transactions on Computers
Analysis and Simulation of Buffered Delta Networks
IEEE Transactions on Computers
The Burroughs Scientific Processor (BSP)
IEEE Transactions on Computers
Bit-Serial Parallel Processing Systems
IEEE Transactions on Computers
The Universality of the Shuffle-Exchange Network
IEEE Transactions on Computers
The Reverse-Exchange Interconnection Network
IEEE Transactions on Computers
On a Class of Multistage Interconnection Networks
IEEE Transactions on Computers
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
A Pipelined Pseudoparallel System Architecture for Real-Time Dynamic Scene Analysis
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
A Model of SIMD Machines and a Comparison of Various Interconnection Networks
IEEE Transactions on Computers
Problems of Designing Supersystems with Dynamic Architectures
IEEE Transactions on Computers
Generalized Connection Networks for Parallel Processor Intercommunication
IEEE Transactions on Computers
Communication Issues in the Design and Analysis of Parallel Algorithms
IEEE Transactions on Software Engineering
Performance Analysis of FFT Algorithms on Multiprocessor Systems
IEEE Transactions on Software Engineering
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
Fault-Tolerant Multiprocessors with Redundant-Path Interconnection Networks
IEEE Transactions on Computers - The MIT Press scientific computation series
Finite State Model and Compatibility Theory: New Analysis Tools for Permutation Networks
IEEE Transactions on Computers
A new interconnection network for SIMD computers: the sigma networks
IEEE Transactions on Computers
On the permutation capability of multistage interconnection networks
IEEE Transactions on Computers
Traffic-Specific Interconnection Networks for Multicomputers
IEEE Transactions on Computers
On the Design of Efficient Multistage Interconnection Networks
MASCOTS '96 Proceedings of the 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
Efficient Protocols for Permutation Routing on All-Optical Multistage Interconnection Networks
ICPP '00 Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing
A General Inside-Out Routing Algorithm for a Class of Rearrangeable Networks
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
A New Tag Scheme and Its Tree Representation for a Shuffle-Exchange Network
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
On Fault-Tolerant Distributor Communication Architecture
IEEE Transactions on Computers
Generalized Hypercube and Hyperbus Structures for a Computer Network
IEEE Transactions on Computers
Packet Switching Networks for Multiprocessors and Data Flow Computers
IEEE Transactions on Computers
Design and Performance of Generalized Interconnection Networks
IEEE Transactions on Computers
Mapping Computation with No Memory
UC '09 Proceedings of the 8th International Conference on Unconventional Computation
On rearrangeability of tandem connection of banyan-type networks
IEEE Transactions on Communications
A novel design of self-routing strictly nonblocking switching networks
International Journal of Computers and Applications
A parallel self-routing rearrangeable nonblocking multi-log2 N photonic switching network
IEEE/ACM Transactions on Networking (TON)
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This paper introduces two graph theoretic models that provide a uniform procedure for analyzing 2n-input/2n-output Multistage Interconnection Networks (MIN's), implemented with 2-input/2-output Switching Elements (SE's) and satisfying a characteristics called the "buddy property." These models show that all such n-stage MIN's are topologically equivalent and hence prove that one MIN can be implemented from integrated circuits designed for another MIN. The proposed techniques also allow identical modeling and comparison of permutation capabilities of n-stage MIN's and other link-controlled networks like augmented data manipulator and SW Banyan Network and hence, allows comparison of their permutation. In the case of any conflict in the MIN, an upper bound for the required number of passes has been obtained.