Distributed fault-tolerance for large multiprocessor systems
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Problem-Solving Methods in Artificial Intelligence
Problem-Solving Methods in Artificial Intelligence
Fault-Tolerant Multiprocessor Link and Bus Network Architectures
IEEE Transactions on Computers
Reliable Loop Topologies for Large Local Computer Networks
IEEE Transactions on Computers
Generalized Hypercube and Hyperbus Structures for a Computer Network
IEEE Transactions on Computers
Graph Theoretical Analysis and Design of Multistage Interconnection Networks
IEEE Transactions on Computers
A Fault-Tolerant Communication Architecture for Distributed Systems
IEEE Transactions on Computers
A Survey of Interconnection Networks
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A new routing algorithm is proposed in this correspondence for the network architecture developed in [1]. It has been shown that this algorithm gives the shortest path between the source to destination, when all the processors and the communication links of the network are non- faulty. For the situation when some of the processors are faulty, a heuristic function is given, which if used in the routing algorithm will give shortest path from the source to destination, if such a path exists.