Switched multiple instruction, multiple data stream processing
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
A design study of a shared resource computing system
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Memory and Bus Conflict in an Array Processor
IEEE Transactions on Computers
The Theory Underlying the Partitioning of Permutation Networks
IEEE Transactions on Computers
IEEE Transactions on Computers
A Parallel Processor Operating System Comparison
IEEE Transactions on Software Engineering
The Theory Underlying the Partitioning of Permutation Networks
IEEE Transactions on Computers
Hi-index | 14.98 |
Performance optimization of a shared-resource parallel computer is studied in this correspondence. Such a parallel computer contains multiple control units (CU's) sharing a resource pool of processing elements (PE's) and operating with multiple single-instruction-multiple-data (MSIMD) streams. A formal queueing model is proposed for MSIMD machines used in multiple array processing. Analytic results are obtained to evaluate the performance of MSIMD computers. Systematic procedures are given to optimize the size of PE resource pool and to determine the sufficient job queue size for a given vector workload distribution.