Some uses of simulation in system design
ANSS '75 Proceedings of the 3rd symposium on Simulation of computer systems
An overview of a multi associative processor study
ACM '74 Proceedings of the 1974 annual conference - Volume 1
The Future of Parallel Processing
IEEE Transactions on Computers
A production implementation of an associative array processor: STARAN
AFIPS '72 (Fall, part I) Proceedings of the December 5-7, 1972, fall joint computer conference, part I
A systematic approach to the design of digital bussing structures
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
The solution of the minimum cost flow and maximum flow network problems using associative processing
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
A parallel processor for evaluation studies
AFIPS '76 Proceedings of the June 7-10, 1976, national computer conference and exposition
STARAN parallel processor system hardware
AFIPS '74 Proceedings of the May 6-10, 1974, national computer conference and exposition
Effects of storage contention on system performance
IBM Systems Journal
Processor autonomy and its effect on parallel program execution
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Microprocessor implementation of a parallel processor
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Resource Optimization of a Parallel Computer for Multiple Vector Processing
IEEE Transactions on Computers
An Optimal Algorithm for Scheduling Requests on Interleaved Memories for a Pipelined Processor
IEEE Transactions on Computers
| Hi-index | 14.99 |
The multiassociative processor (MAP) system is a hypothetical machine composed of eight control units (CU's) and an arbitrary number of processing elements (PE's). Each CU is allocated a subset of the identical PE's in order to process a single-instruction-stream-multiple-data-stream program. The eight CU's must be able to access a common main memory system and transmit data to subsets of the PE's over a shared data bus system. This paper discusses the analysis of these two components of the system where this analysis relies heavily on three simulation programs. The first program interprets assembly language programs for the hypothetical machine and the other two programs model the memory system and the data bus system. The interpreter is driven by both realistic array processor programs and synthetic programs designed specifically to test the components of the system.