IEEE Transactions on Pattern Analysis and Machine Intelligence - Special Issue on Industrial Machine Vision and Computer Vision Technology:8MPart
Introducing local autonomy to processor arrays
Machine Vision: Algorithms, Architectures, and Systems
Connection autonomy in SIMD computers: a VLSI implementation
Journal of Parallel and Distributed Computing
BLITZEN: a highly integrated massively parallel machine
Journal of Parallel and Distributed Computing - Massively parallel computation
NAP (No ALU processor): the great communicator
Journal of Parallel and Distributed Computing - Massively parallel computation
Introduction to algorithms
Processor Arrays: Architecture and Applications
Processor Arrays: Architecture and Applications
Memory and Bus Conflict in an Array Processor
IEEE Transactions on Computers
IEEE Transactions on Computers
The UCSC Kestrel Parallel Processor
IEEE Transactions on Parallel and Distributed Systems
A low-cost mixed-mode parallel processor architecture for embedded systems
Proceedings of the 21st annual international conference on Supercomputing
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Processor autonomy is the potential of a processing element in a parallel computer to act differently from other processors during execution. A new parallel architecture taxonomy is presented that includes the necessary and sufficient conditions to achieve processor autonomy. Processor autonomy is possible when multiple data address, data value, instruction address, or instruction value streams are available. Parallel program execution can be significantly aided by processor autonomy, allowing various mappings and dynamic reassignment of PEs to streams. Parallel program performance is evaluated for several sorting algorithms using one form of data address autonomy, indirect addressing, and one form of instruction value autonomy, branch selection.