Performance Evaluation and Monitoring
ACM Computing Surveys (CSUR)
A Survey of Some Theoretical Aspects of Multiprocessing
ACM Computing Surveys (CSUR)
The nucleus of a multiprogramming system
Communications of the ACM
Some uses of simulation in system design
ANSS '75 Proceedings of the 3rd symposium on Simulation of computer systems
IEEE Transactions on Computers
ILLIAC IV Software and Application Programming
IEEE Transactions on Computers
Measurement and analysis of large operating systems during system development
AFIPS '68 (Fall, part I) Proceedings of the December 9-11, 1968, fall joint computer conference, part I
A production implementation of an associative array processor: STARAN
AFIPS '72 (Fall, part I) Proceedings of the December 5-7, 1972, fall joint computer conference, part I
Memory and Bus Conflict in an Array Processor
IEEE Transactions on Computers
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The Multi Associative Processor system is a multiple control unit parallel processor capable of executing a maximum of 8 single-instruction-stream, multiple-data-stream programs simultaneously. The architecture supports parallelism at two levels: the lower level is the tightly coupled parallelism typical of array processors, and the higher level is the more loosely coupled parallelism between independent processes. The architecture of the machine is described and an example program for the machine is given to illustrate many of the concepts of the architecture. Measurement and evaluation studies on the machine are also briefly discussed.