A high efficient on-chip interconnection network in SIMD CMPs

Authors:
Dan Wu;Kui Dai;Xuecheng Zou;Jinli Rao;Pan Chen
Affiliations:
Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan, China;Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan, China;Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan, China;Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan, China;Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan, China
Venue:
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Year:
2010

Citing 17
Cited 0

Clock rate versus IPC: the end of the road for conventional microarchitectures

Proceedings of the 27th annual international symposium on Computer architecture
MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications

IEEE Transactions on Computers
Will Physical Scalability Sabotage Performance Gains?

Computer
Imagine: Media Processing with Streams

IEEE Micro
A 10 GIPS SIMD Processor for PC-based Real-Time Vision Applications --- Architecture, Algorithm Implementation and Language Support

CAMP '97 Proceedings of the 1997 Computer Architectures for Machine Perception (CAMP '97)
A cellular computer to implement the kalman filter algorithm

A cellular computer to implement the kalman filter algorithm
Understanding the efficiency of GPU algorithms for matrix-matrix multiplication

Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling

Proceedings of the 32nd annual international symposium on Computer Architecture
Interconnect-Aware Coherence Protocols for Chip Multiprocessors

Proceedings of the 33rd annual international symposium on Computer Architecture
Design tradeoffs for tiled CMP on-chip networks

Proceedings of the 20th annual international conference on Supercomputing
Design of a Massively Parallel Processor

IEEE Transactions on Computers
The ILLIAC IV Computer

IEEE Transactions on Computers
GRAPE-DR: 2-Pflops massively-parallel computer with 512-core, 512-Gflops processor chips for scientific computing

Proceedings of the 2007 ACM/IEEE conference on Supercomputing
Parallel FFT Algorithms on Network-on-Chips

ITNG '08 Proceedings of the Fifth International Conference on Information Technology: New Generations
An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

The Journal of Supercomputing
An energy and performance exploration of network-on-chip architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing area and performance constrained SIMD/VLIW image processing architectures

ACIVS'05 Proceedings of the 7th international conference on Advanced Concepts for Intelligent Vision Systems

Quantified Score

Hi-index	0.01

Visualization

Abstract

In order to improve the performance of on-chip data communications in SIMD (Single Instruction Multiple Data) architecture, we propose an efficient and modular interconnection architecture called Broadcast and Permutation Mesh network (BP-Mesh) BP-Mesh architecture possesses not only low complexity and high bandwidth, but also well flexibility and scalability Detailed hardware implementation is discussed in the paper And the proposed architecture is evaluated in terms of area cost and performance.