PAVLOV: a programmable architecture for volume processing
HWWS '98 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Interactive volume segmentation with the PAVLOV architecture
PVGS '99 Proceedings of the 1999 IEEE symposium on Parallel visualization and graphics
Fast and Accurate Robot Vision for Vision Based Motion
RoboCup 2000: Robot Soccer World Cup IV
RoboCup 2000: Robot Soccer World Cup IV
Array control for high-performance SIMD systems
Journal of Parallel and Distributed Computing
A New Real Time Object Segmentation and Tracking Algorithm and its Parallel Hardware Architecture
Journal of VLSI Signal Processing Systems
A new real time object segmentation and tracking algorithm and its parallel hardware architecture
Journal of VLSI Signal Processing Systems
RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications
Journal of Embedded Computing - Issues in embedded single-chip multicore architectures
A high efficient on-chip interconnection network in SIMD CMPs
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
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This paper describes hardware implementation and software environment of a one-dimensional SIMD processor, IMAP-VISION. IMAP-VISION board is a single-slot PCI-bus board designed for PC-based real-time vision applications. The SIMD processor consists of 256 8-bit linear processor array and has 10.24 GIPS peak performance. In this paper, some detailed algorithm implementations, those which make use of IMAP-VISION special functions, are described, as well as IMAP-VISION architecture, hardware implementation, performance figures and software environment including high-level language 1DC and graphical user interface.