The connection machine
IEEE Transactions on Pattern Analysis and Machine Intelligence
The DARPA image understanding benchmark for parallel computers
Journal of Parallel and Distributed Computing
The evaluation of massively parallel array architectures
The evaluation of massively parallel array architectures
System design for pixel-parallel image processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issues in the Design of High Performance SIMD Architectures
IEEE Transactions on Parallel and Distributed Systems
A system for evaluating performance and cost of SIMD array designs
Journal of Parallel and Distributed Computing
Morphological Image Processing: Architecture and VLSI Design
Morphological Image Processing: Architecture and VLSI Design
A 64 parallel integrated memory array processor and a 30 GIPS real-time vision system
CAMP '95 Proceedings of the Computer Architectures for Machine Perception
The Design of Highly-Parallel Image Processing Systems Using Nanoelectronic Devices
CAMP '97 Proceedings of the 1997 Computer Architectures for Machine Perception (CAMP '97)
A general purpose SliM-II image processor
CAMP '97 Proceedings of the 1997 Computer Architectures for Machine Perception (CAMP '97)
The CC/IPP, an MIMD-SIMD architecture for image processing and pattern recognition
CAMP '97 Proceedings of the 1997 Computer Architectures for Machine Perception (CAMP '97)
CAMP '97 Proceedings of the 1997 Computer Architectures for Machine Perception (CAMP '97)
Processor/Memory/Array Size Tradeoffs in the Design of SIMD Arrays for a Spatially Mapped Workload
CAMP '97 Proceedings of the 1997 Computer Architectures for Machine Perception (CAMP '97)
Making a Dataparallel Language Portable for Massively Parallel Array Computers
CAMP '97 Proceedings of the 1997 Computer Architectures for Machine Perception (CAMP '97)
A Dedicated Image Processor Exploiting both Spatial and Instruction-Level Parallelism
CAMP '97 Proceedings of the 1997 Computer Architectures for Machine Perception (CAMP '97)
Three Dimensional Graphics Algorithms for the Micro Grain Array Processor-II
CAMP '97 Proceedings of the 1997 Computer Architectures for Machine Perception (CAMP '97)
High Speed Target Tracking Vision Chip
CAMP '00 Proceedings of the Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00)
Parallel Segmentation Based on Topology with the Associative Net Model
CAMP '00 Proceedings of the Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00)
2-D Object Recognition by Structured Neural Networks in a Pyramidal Architecture
CAMP '00 Proceedings of the Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00)
Abacus: a reconfigurable bit-parallel architecture for early vision
Abacus: a reconfigurable bit-parallel architecture for early vision
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Although arrays of SIMD processing elements can be built with very high operating frequencies, problems exist in keeping the array busy. The inherent mismatch between host and array makes it difficult to maintain high array utilization: either the rate of instruction issue is very low or PE data locality is compromised, having the same effect. Our solution is based on an array control unit (ACU) design that expands macroinstructions in two stages, first by data tile and then into microinstructions. The expansion itself solves the issue problem; decoupling the expansion modalities maintains data locality. Several issues involving host/ACU interaction need to be resolved to effect this solution. We present experimental results showing that our approach delivers substantial improvement in memory hierarchy performance: a cache of only one-fourth the size is sufficient to achieve the same performance as previous approaches. We also describe our implementations which demonstrate that achieving gigaherz operating frequencies with current technologies is plausible.