PAVLOV: a programmable architecture for volume processing
HWWS '98 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Interactive volume segmentation with the PAVLOV architecture
PVGS '99 Proceedings of the 1999 IEEE symposium on Parallel visualization and graphics
Array control for high-performance SIMD systems
Journal of Parallel and Distributed Computing
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The paper presents a new version of the sliding memory plane image processor (SliM-II) which integrates a linear array of sixty-four 8-bit processing elements (PEs) on a single chip. In contrast to existing SIMD array processors, each PE has a multiplier that is quite effective for correlation, convolution, template matching, etc. The instruction set can execute an ALU/multiplier operation, a parallel move operation, an inter-PE communication operation, and a data I/O operation simultaneously in an instruction cycle. Moreover, SliM-II has special features, such as an adder tree for histogramming, a sum-or tree for program control, etc. SliM-II operates at 30 MHz in the worst case simulation, and thus, gives at least 1.92 GIPS. The total number of transistors is about 1.5 millions, the core size is 13.2/spl times/13.0 mm/sup 2/ and the package type is 208 pin PQ2.