The ILLIAC IV Processing Element

  • Authors:
  • R. L. Davis

  • Affiliations:
  • -

  • Venue:
  • IEEE Transactions on Computers
  • Year:
  • 1969

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Abstract

This paper describes the design of the processing element (PE) of I IV, a parallel processing computer consisting of 256 PE's, each with an associated 2048 word memory. Each PE-memory combination with its data-dependent controls is a computer in itself, devoid of those controls common to all PE-memory combinations, such as instruction decoding, instruction look-ahead, etc.