AFIPS '62 (Fall) Proceedings of the December 4-6, 1962, fall joint computer conference
The ILLIAC IV Processing Element
IEEE Transactions on Computers
AFIPS '63 (Fall) Proceedings of the November 12-14, 1963, fall joint computer conference
Some applications for content-addressable memories
AFIPS '63 (Fall) Proceedings of the November 12-14, 1963, fall joint computer conference
AFIPS '66 (Fall) Proceedings of the November 7-10, 1966, fall joint computer conference
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The SOLOMON computer has a novel design which is intended to give it unusual capabilities in certain areas of computation. The arithmetic unit of SOLOMON is constructed with a large number of simple processing elements suitably interconnected, and hence differs from that of a conventional computer by being capable of a basically parallel operation. The initial development and study of this new computer has led to considerable scientific and engineering inquiry in three problem areas: 1. The design, development, and construction of the hardware necessary to make SOLOMON a reality. 2. The identification and investigation of numerical problems which most urgently need the unusual features of SOLOMON. 3. The generation of computational techniques which make the most effective use of SOLOMON'S particular parallel construction. This paper is an early report on some work which has been done in the second and third of these areas. SOLOMON has certain inherent speed advantages as a consequence of its design. In the first place, computers conventionally require two memory cycles per simple command--one cycle to obtain the instructions and one cycle to obtain the operand. Although SOLOMON has the same basic requirement it handles up to 1024 operands with each instruction. Consequently, the time per operand spent in obtaining the instruction is negligible. This results in increasing the speed by a factor of two. In the second place, the fact that the processing elements handle 1024 operands at once greatly increases the effective speed. The factor is not 1024, however. Since the processors are serial-by-bit they require n memory references to add an n-bit word. If n is taken nominally to be 32, then the resulting net speed advantage is 1024/n, that is 1024/32 = 32. These two factors result in a fundamental speed increase on the order of 64 to 1 for comparable memory cycle times. In addition to these concrete factors, there are other factors whose contribution to speed cannot be as easily measured. Among these are i) the advantages due to the intercommunication paths between the processing elements, ii) the advantage of using variable word length operations, iii) the net effect resulting from either eliminating conventional indexing operations or else superseding them by mode operations, and iv) the loss in effectiveness resulting from the inability of utilizing all processors in every operation. The net speed advantage can only be determined by detailed analysis of individual specific problems. The task of evaluating the feasibility of the SOLOMON computer has led to investigations of problems which primarily involve elementary, simultaneous computations of an iterative nature. In particular, the solution of linear systems and the maintenance of real-time multi-dimensional control and surveillance situations have been considered. Within these very broad areas two special problems have been rather thoroughly studied and are presented here to demonstrate the scope and application of SOLOMON. The first of these is a problem from partial differential equations, namely the discrete analogue of Dirichlet's problem on a rectangular gird. The second is the real-time problem of satellite tracking and the computations which attend it. These problems are discussed here individually and are followed by a brief summation of other work.