A microprocessor-controlled asynchronous circuit switching network
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Study of multistage SIMD interconnection networks
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
A class of modified single stage S/E networks
CSC '86 Proceedings of the 1986 ACM fourteenth annual conference on Computer science
The Universality of a Class of Modified Single-Stage Shuffle/Exchange Networks
IEEE Transactions on Computers
Performance and fault tolerance improvements in the Inverse Augmented Data Manipulator network
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
The Extra Stage Cube: A Fault-Tolerant Interconnection Network for Supersystems
IEEE Transactions on Computers
International Journal of Modelling and Simulation
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From the reliability point of view, the uniqueness of path between any processor and memory module in a standard k-column Shuffle/Exchange (S/E) network is an inherent weakness. It is proposed to add a column of switches to the existing multistage S/E network such that the modified network, which will be called the S/E-Plus network, will retain the permuting power of the corresponding S/E network and have dual paths between any processor and any memory module. Fault tolerant routing algorithm is then designed to exploit the dual path structure of the S/E-Plus network. Various applications of the routing algorithm including a technique for performing permutation in the S/E-Plus network in which a fault exists are also discussed. Finally, the path reliability and the path reliability gain are defined to evaluate the S/E-Plus network.