Switched multiple instruction, multiple data stream processing
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
Parallel Processing with the Perfect Shuffle
IEEE Transactions on Computers
Data Manipulating Functions in Parallel Processors and Their Implementations
IEEE Transactions on Computers
The Indirect Binary n-Cube Microprocessor Array
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
Generalized Connection Networks for Parallel Processor Intercommunication
IEEE Transactions on Computers
An organization for optical linkages between integrated circuits
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
An overview of the Texas reconfigurable array computer
AFIPS '80 Proceedings of the May 19-22, 1980, national computer conference
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
The Extra Stage Cube: A Fault-Tolerant Interconnection Network for Supersystems
IEEE Transactions on Computers
Organization of the TRAC processor-memory subsystem
AFIPS '80 Proceedings of the May 19-22, 1980, national computer conference
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Over the past few years, owing to technological breakthroughs in building cheap, reliable and powerful microprocessors and relatively cheap LSI memories, interconnection networks have become the major hardware cost in design and implementation of the multiprocessor systems. This situation occurs from the fact that many more functions may be expected from the interconnection network (switch) than the establishment of simple bus connections. Even if only the communication links were considered, the complexity of some networks make their implementation prohibitive. An example of such a network is a crossbar whose complexity is 0(n**2) where n represents a number of resources which may be connected to another set of n resources. This switch provides a separate connection between each pair of resources (Figure 1). It has been empirically shown that implementation of a crossbar switch for a large n is very difficult and with a state-of-the-art technology practically infeasible for n50.