Data Manipulating Functions in Parallel Processors and Their Implementations
IEEE Transactions on Computers
The Indirect Binary n-Cube Microprocessor Array
IEEE Transactions on Computers
The Reverse-Exchange Interconnection Network
IEEE Transactions on Computers
On a Class of Multistage Interconnection Networks
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
The Load-Sharing Banyan Network
IEEE Transactions on Computers
Fault-Tolerant Single-Stage Interconnectiohl Networks
IEEE Transactions on Computers
ICPP '97 Proceedings of the international Conference on Parallel Processing
A fault location technique and alternate routing in Benes network
ATS '95 Proceedings of the 4th Asian Test Symposium
Performance analysis and fault tolerance of randomized routing on Clos networks
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Design of a 2 × 2 fault-tolerant switching element
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Diagnosing crosstalk-faulty switches in photonic networks
SRDS '96 Proceedings of the 15th Symposium on Reliable Distributed Systems
IEEE Transactions on Computers
The Extra Stage Cube: A Fault-Tolerant Interconnection Network for Supersystems
IEEE Transactions on Computers
Hi-index | 14.99 |
To study the fault-diagnosis method for a class of multistage interconnection networks a general fault model is first constructed. Specific steps for diagnosing single faults and detecting multiple faults in interconnection networks such as the indirect binary n-cube network and the flip network are then developed. The following results are derived in this study: 1) independent of the network size, only four tests are required for detecting a single fault; 2) the number of tests required for locating a single fault and determining the fault type ranges from 4 to max(12, 6 + 2 ?log2(log2N)?) except for four types of single faults in the switching elements which cannot be pinpointed at the switching element level where N is the number of inputs/outputs; 3) only four tests are required for locating a single fault if the switching element is designed in such a way that any physical defection of the switching element causes both outputs of the related switching element to be faulty; and 4) multiple faults can be detected by 2(1 + log2N) tests.