On the multiple fault diagnosis of multistage interconnection networks: the lower bound and the CMOS fault model

Authors:
Y.-N. Shen;Xiao-Tao Chen;Susumu Horiguchi;Fabrizio Lombardi
Affiliations:
-;-;-;-
Venue:
ICPP '97 Proceedings of the international Conference on Parallel Processing
Year:
1997

Citing 5
Cited 0

Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits

IEEE Transactions on Computers
Logic design principles with emphasis on testable semicustom circuits

Logic design principles with emphasis on testable semicustom circuits
On the Constant Diagnosability of Baseline Interconnection Networks

IEEE Transactions on Computers
Detection and Location of Multiple Faults in Baseline Interconnection Networks

IEEE Transactions on Computers
Fault-Diagnosis for a Class of Multistage Interconnection Networks

IEEE Transactions on Computers

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents new results for diagnosing (detection and location) multistage interconnection networks (MINs) in the presence of multiple faults. Initially, it is proved that the lower bound in the number of tests for multiple fault diagnosis (independent of the assumed fault model for the MIN) is 2/spl times/log/sub 2/N, where N is the number of inputs/outputs of the network. A new fault model is introduced; this fault model is applicable to interconnection networks implemented using CMOS technology. The characterization for diagnosing stuck-open faults is presented.