Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
Parallel computing: theory and comparisons
Parallel computing: theory and comparisons
On the Constant Diagnosability of Baseline Interconnection Networks
IEEE Transactions on Computers
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
Computational Aspects of VLSI
Design and Performance Analysis of Load-Distributing Fault-Tolerant Network
IEEE Transactions on Computers
Distributed Fault Diagnosis in Multistage Network-Based Multiprocessors
IEEE Transactions on Computers
ICPP '97 Proceedings of the international Conference on Parallel Processing
Concurrent fault detection for a multiple-plane packet switch
IEEE/ACM Transactions on Networking (TON)
Testing Layered Interconnection Networks
IEEE Transactions on Computers
Performance Evaluation of a Fault-Tolerant Switch for Next Generation Computer Networks
ICPADS '06 Proceedings of the 12th International Conference on Parallel and Distributed Systems - Volume 2
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An algorithm for fault diagnosis (detection and location) of baseline interconnection networks in the presence of multiple faults is presented. This algorithm requires 2(1+log/sub 2/ N) tests, where log/sub 2/ N is the number of stages. Multiple fault diagnosis is possible provided: (a) there exists no logically erroneous and unidentified outputs in each faulty switching element and (b) multiple link faults (of the type stuck-at-0 stuck-at-1) do not exist in the network. Fault location is accomplished using an iterative process which checks each stage of the multistage interconnection network. A new functional description of the network is introduced to facilitate fault location.