Shift Register Sequences
A Modular Approach to Real-Time Supersystems
IEEE Transactions on Computers
A Multicomputer System with Dynamic Architecture
IEEE Transactions on Computers
Problems of Designing Supersystems with Dynamic Architectures
IEEE Transactions on Computers
The Software Development System
IEEE Transactions on Software Engineering
Reconfiguration Procedures for a Polymorphic and Partitionable Multiprocessor
IEEE Transactions on Computers
IEEE Transactions on Computers
Design and Evaluation of a Multiprocessor Architecture with Decentralized Control
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Data Exchange Optimization in Reconfigurable
IEEE Transactions on Computers
Efficient Internode Communications in Reconfigurable Binary Trees
IEEE Transactions on Computers
Reconfigurable fault-tolerant multicomputer network
AFIPS '83 Proceedings of the May 16-19, 1983, national computer conference
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This paper introduces concurrent reconfiguration techniques that perform fast reconfiguration of a multicomputer network into the following network structures: K-rooted trees, stars, and rings with selectable periods. These structures prove to be very efficient for high-speed, real-time applications. The techniques introduced are based on shift register theory and are performed by special shift registers residing in each network node and called shift registers with variable bias. The technique discussed in this paper are implemented in the system with dynamic architecture that is now under construction by Dynamic Computer Architecture, Inc. The time of the network reconfiguration equals that of one clock period, since to perform reconfiguration into a new network structure, each network node should execute only two logical operations---one-bit shift and mod 2 addition.