An introduction to the boundary scan standard: ANSI/IEEE Std 1149.1
Journal of Electronic Testing: Theory and Applications
Memory testing in a massively parallel machine
EUROMICRO 93 Nineteenth EUROMICRO symposium on microprocessing and microprogramming on Open system design : hardware, software and applications: hardware, software and applications
The Test Access Port and Boundary-Scan Architecture
The Test Access Port and Boundary-Scan Architecture
Functional Testing and Reconfiguration of MIMD Machines
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
A Routing Testing of a VLSI Massively Parallel Machine Based on IEEE 1149.1
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
EXECUBE-A New Architecture for Scaleable MPPs
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
A Complete Strategy for Testing an On-Chip Multiprocessor Architecture
IEEE Design & Test
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This paper presents an implementation approach for thetest of routers in a fine grain massively parallel architecture.First, an ad hoc test technique which diffuses test messagesrouter by router is analyzed. Even though the technique does notadd hardware, it is shown inefficient and not applicable due topractical constraints such as the limited number of pins of thechip implementing the machine. Based on a hierarchicalimplementation of the IEEE 1149.1 standard, two approaches areproposed and compared in terms of the area overhead, the overalltest time and the flexibility in applying tests and diagnosingthe routers inside the machine. The basic idea for bothapproaches is to construct groups of basic cells which aredriven by the same test block and compare their test resultsafter the same test vectors are applied at each cell input. Thetwo approaches differ in the granularity of a basic cell. Thechoice of an implementation approach is not trivial. It is shownthat each approach presents better performance than the other,that is, the approach which allows better fault coverage and lesstest time requires more silicon and less diagnosticpossibilities compared to the second approach.